In a one-bit type EEPROM (electrically erasable programmable read only memory) cell, a device isolation layer 13 defining an active region and a device isolation region is formed in a substrate 11. A tunnel oxide 15 and a floating gate 17 are layered in the active region. In other words, the one-bit cell includes one floating gate per cell. The device isolation layer is formed through a LOCOS (local oxidation of silicon) or an STI (shallow trench isolation) process.
On the other hand, a two-bit type cell comprises two floating gates per cell. FIG. 1 is a cross-sectional view of a conventional EEPROM cell of the two-bit type. The two-bit type of EEPROM cell can share two (2) floating gates in one cell, whereas the one-bit type of EEPROM cell includes one floating gate in one cell.
However, in the prior art, when two floating gates have been formed in one cell, the cell size has increased as large as the lithographic minimum feature size (hereinafter referred to as “F”), such as a space size between the two floating gates. The minimum size of “F” is irrelevant to the smooth operation of a cell. Rather it is necessarily caused by limitations of the mask patterning. Therefore, it is preferable to reduce the “F” value in order to decrease cell size.